DRAM (DDRx LPDDRx) Architecture

Course Objectives:

Ever since Intel introduced DRAM memory, it has evolved in size, density, speed and architecture. It has also evolved in power consumption, most notably with the Low-Power DDRs. DRAMs have evolved to DDR4 and LPDDR4. This DRAM Architecture course describes the development of computer memory systems and covers in-depth today’s most advanced DRAM technology. The course ultimately focuses on ultra-dense, high-speed DDR3/DDR4/LPDDR3/LPDDR4 technology. Memory cell theory, operation and key device architecture differences from SDRAM through DDR4 as well as LPDDR1 through LPDDR4 are covered. The PC DIMM organization is covered, as well as bus implementations. Initialization of a memory channel is described. System design challenges, ranging from signal routing to error handling, are covered. Using waveform examples, state diagrams and truth tables, the commands and correct sequencing of operations are taught. DRAM controller design principles are also discussed. Upon completion of this training, participants will acquire knowledge and skills on:

  1. How a DRAM array is organized
  2. Organization of a variety of memory modules
  3. How to understand DRAM transaction waveforms so that you can debug a memory channel
  4. How to refresh a DRAM
  5. Electrical characteristics of DDRx and LPDDRx signals
  6. Elements of DRAM controller design
  7. Differences between DDR1 through DDR4 as well as LPDDR1 through LPDDR4
  8. DRAM power management
  9. Error handling

Course Outline:
Day 1 – 3:

  1. System Architecture
  2. Back to the Future DRAM Intro
  3. DRAM Cell Architecture
  4. DRAM Device Architecture
  5. DDRx/LPDDRx Feature Summary, Comparison, and Roadmap
  6. DRAM Controller Basics
  7. Packaging DDR3, DDR4, LPDDR3, LPDDR4, WideIO
  8. DDR3 and DDR4 Module Architecture
  9. Device and Module Pin Descriptions
  10. Commands and Waveforms
  11. Refresh
  12. Electrical Specifications
  13. Power Management
  14. Introduction to Signal Integrity Issues
  15. Signal Routing
  16. On-Die Termination
  17. Initialization, Calibration, and Training
  18. Errors and Error Handling
  19. Introduction to Testing

Who Should Attend:
This course is hardware centric but does describe DRAM memory and DRAM controller initialization. It is suitable for hardware engineers, but software/firmware engineers will benefit. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers.

Date of Programme:
01 - 03 Nov 2017

Time:
09.00am – 5.30pm

Venue:
16 Jalan Kilang #03-05 Singapore 159416

Course Fees:
S$3,099

How to Register:
Please register at: http://www.wizlogix.com/event/detail/modern-dram-architecture.

UTAP Details:
NTUC Members enjoy 50% unfunded course fee support for up to *$250 each year when you sign up for courses supported under UTAP (Union Training Assistance Programme). *Conditions apply

Please visit our website at http://skillsupgrade.ntuc.org.sg for more information. Funding for approved courses only.

Training Provider:

Close